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Si5040
aLOSThresh (Bit 1:0, Register 13 and Bit 7:0, Register 12)
aLOSHyst[3:0] (Bit 7:4, Register 13)
Peak-to-
Peak
aLOS
(Bit 1, Register 11)
Monitor
aLosEn
(Bit 0, Register 10, Default= 1)
RxdLosAssertThresh[7:0] (Bit 7:0, Register 17)
RxdLosClearThresh (Bit 7:0, Register 18)
LOS
00:
01:
01:
01:
DLOS
Monitor
EN
dLosEn[1:0]
(Bit 2:1, Register 10)
Disabled (Default)
Based on consecutive number of 1s
Based on consecutive number of 0s
Based on either consecutive number of 1s or 0s
RxSqmThresh[5:0] (Bit 7:2, Register 26)
RxSqmDeassertThresh[5:0] (Bit 5:0, Register 27)
dLOS
(Bit 2, Register 11)
(Bit 5, Register 9,
Bit 0, Register 11 or Pin 3)
1
EN
Signal
Quality
Monitor
sqmAlarm
(Bit 0, Register 9)
sqmLOS
(Bit 4, Register 11)
RxSqmValue[5:0]
sqmLosEn
(Bit 3, Register 10, Default= 0)
lolOnLos
(Bit 6, Register 7, Default= 0)
(Bit 5:0, Register 25)
SqmLol
1 (Default)
LOL
(Bit 4, Register 9 or Pin 2)
Rx Recovered Clock
Frequency
Offset
FreqLol
0
Reference Clock
Monitor
Select
useLolMod
lolMode
(Bit 3, Register 7, Default= 0)
(Bit 2, Register 7)
Figure 15. RX LOS and LOL Block Diagram
26
Rev. 1.3
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